Digital to analog converters are used in a wide variety of electronic systems where it is necessary to convert a group of digital data samples or words into a corresponding analog signal. A typical application for a D/A converter is in a pulse code modulated speech system where digital codes are transmitted over some distance to a device for reproducing the digital codes as analog speech sounds. In these and other types of applications it is important that the D/A conversion process is as accurate as possible. Unfortunately, electrical noise in the incoming digital data tends to increase the potential for error. Where the digital data is transmitted at great distances from a remote data source this potential for error is especially great.
State of the art D/A converters examine each symbol or bit in the digital word and make an unambiguous decision as to the state of that bit (i.e. 0 or 1 if a binary symbol; 0, 1 or 2 if ternary, etc.). In other words, even if the received voltage level associated with a bit does not correspond to the defined voltage level for either a logical 1 or logical 0 level, the present day converters must make a hard and fast decision as to whether that bit is really a logical 1 or logical 0. The analog value of the digital word is obtained by applying appropriate weighting factors to each bit position in the word and summing together all of the resulting weighted values. For example, if the digital word has n bits in a typical binary code, the analog value of that word is given by ##EQU1## where X.sub.k is a binary variable, either 0 or 1.
For example, if the digital word comprises four bits, the least most significant bit (k=1) is weighted with a value of 1, the second least most significant bit (k=2) is weighted with a value of 2, the third least most significant bit (k=3) is weighted with a value of 4, and the most significant bit (k=4) is weighted with a value of 8.
To perform the operation given by equation (1) a decision has to be made as to the one or zero state of each X.sub.k variable. In an idealized communication system this task poses no problem. However, in the real world this is another matter. Consider, for example, the case where digitized speech samples are transmitted over a noisy channel. In such instances some of the decisions as to whether each bit is a one (or zero) will be wrong because the instantaneous value of the noise added to the binary information signal may cause a one to be misinterpreted as a zero, or a zero to be misinterpreted as one. These interpretation errors will therefore result in an error in the analog signal produced by the D/A converter, the magnitude of the error being related to the relative weight of the erroneously interpreted bit in its respective digital word. If the misinterpretation error occurred for the most significant bit having a weighting factor of 8, the resulting analog signal error will be substantial.
Although conventional D/A converters utilize a variety of hardware techniques for accomplishing the operation just described, one commonly employed implementation is illustrated in FIG. 1. Serial digital data is received over input line 10. The incoming data signal is a composite of the idealized information signal (S) generated by the data source and electrical noise (N). FIG. 2 illustrates a four-bit digital word comprised of a binary sequence of ones and zeroes, normalized so that binary one is represented as a +1 volt level and a binary zero is represented as a -1 volt level. In the presence of additive noise, the composite waveform (S+N) will take on additional values other than +1 or -1 volts as a function of time. If the noise has a zero means value, one decision rule that may be employed by circuitry 12 of conventional converters is to call a bit logical one if it has a positive polarity and call a bit a logical zero it if has a negative polarity. Such a hard decision criteria is particularly suceptible to errors where the voltge "a" for a given bit period is close to zero volts as shown for the most significant bit position in FIG. 2. Using conventional D/A techniques, one is forced to assign a value of one or zero to that bit even though the probability that it should be assigned to the other state is nearly 0.5. It can be seen that the voltage level, a, for the examined bit position may result from a binary one information signal (-1 volt) combined with a negative noise voltage, e.sub.nl. Alternatively, it can result from a binary zero (-1 volt) added to a positive noise voltage, e.sub.n2, as also illustrated in FIG. 2. Consequently, in half the instances where such a situation exists, no error in the analog reconstruction will be experienced whereas in the other half there will be an error of a magnitude of 2.sup.k-1 where 1.ltoreq.k.ltoreq.n.
The decision circuitry 12 continues to make these hard decisions for each bit of the received data word, sequentially loading the results into register 14. At the end of the decision process for each word the bit values contained in register 14 are coupled simultaneously in parallel to appropriately weighted analog multiplication circuits 16 whose outputs are summed together by summing device 18 to generate the analog signal. It can be seen that the multiplication circuits 16 are weighted according to the significance of the bit to which it is associated. For example, the most significant bit in our four-bit data word example will be weighted for the value of 2.sup.3 or 8. Again, it can be seen that an error in interpreting the state of the most significant bit results in a dramatic error in the generated analog signal. In instances such as those described above, the magnitude of the error will therefore be ##EQU2## The mean squared error will be: ##EQU3##
Note that the mean squared error is greater than the square of the mean error. In fact, ##EQU4##
Thus, it can be seen that errors of some appreciable magnitude can be experienced in using the so-called "hard decision" process employed by conventional digital to analog conveters. The present invention is directed to solving these problems and reducing the potential for error.